The present invention relates to a charge pump circuit for generating a voltage on an integrated circuit device. More specifically, the present invention relates to an output stage for a charge pump circuit that provides a DC voltage output that approaches the maximum high (breakdown) voltage of a CMOS device.
FIG. 1 is a block diagram of a conventional voltage generator 100 used to generate a DC voltage, greater than the VCC supply voltage, on an integrated circuit chip. Voltage generator 100 includes synchronizer 101, charge pump 102 and output stage 103. Synchronizer 101 provides a clock signal CLK having a frequency of FCLK to charge pump 102. In response, charge pump 102 generates a charge pump output voltage VCH having an amplitude of VCHxe2x80x94MAX and a frequency of FCLK. Also in response to the CLK signal, charge pump 102 provides a switching signal VSW having a frequency of FCLK. The VCH and VSW signals are provided to output stage 103.
Output stage 103 includes NMOS transistor 111, capacitor 112 and output terminal 113. The source of NMOS transistor 111 is coupled to receive the VCH signal, the gate of NMOS transistor 111 is coupled to receive the VSW signal, and the drain of NMOS transistor is coupled to output terminal 113. The bulk of NMOS transistor 111 is coupled to ground. Capacitor 112 is coupled between the drain of NMOS transistor 112 and ground. The output voltage VOUT is provided on output terminal 113.
Voltage generator 100 operates as follows. Shortly after the VCH signal transitions to a high state, the VSW signal transitions to a high state, thereby turning on NMOS transistor 111 and charging capacitor 112. The VSW signal subsequently transitions to a low state, thereby turning off NMOS transistor 111. Shortly thereafter, the VCH signal transitions to a low state. At this time, capacitor 112 discharges. Capacitor 112 ensures that a relatively constant DC output voltage VOUT is provided on output terminal 113.
The maximum output voltage VOUT is undesirably limited by the characteristics of NMOS transistor 111. NMOS transistor 111 has a maximum high voltage VMAX (i.e., breakdown voltage) that cannot be exceeded, or the transistor will be damaged. The maximum output voltage VOUT is equal to the breakdown voltage VMAX minus the threshold voltage of transistor 111 (VTH) and the body effect. Thus, if the maximum voltage VMAX of NMOS transistor 111 is 12 Volts, and the threshold voltage VTH and body effect of NMOS transistor 111 is 2 Volts, then the output voltage VOUT is limited to only 10 Volts.
Note that NMOS transistor 111 cannot simply be replaced by a PMOS transistor because the source-to-bulk junction and the drain-to-bulk junction of the PMOS transistor would become forward biased. thereby preventing proper charging and discharging of capacitor 112.
It would therefore be desirable to have a voltage generating circuit that is capable of overcoming the deficiencies of the above-described circuit.
Accordingly, the present invention provides a voltage generation circuit having an improved output stage, which allows the maximum output voltage to closely approximate the breakdown voltage of a CMOS transistor.
An output stage of the present invention includes a first PMOS transistor having a source region and a bulk region coupled to receive the charging voltage signal VCH from a corresponding charge pump. The charging voltage VCH periodically transitions between a low charging voltage VCHxe2x80x94MIN and a high charging voltage VCHxe2x80x94MAX. The first PMOS transistor further includes a drain region coupled to a first node, and a gate coupled to receive a switching voltage signal VSW.
A second PMOS transistor is connected in series with the first PMOS transistor. More specifically, the second PMOS transistor includes a drain region coupled to the first node, a gate coupled to receive the switching voltage signal VSW, and a source region and a bulk region coupled to an output terminal.
A capacitor is coupled between the output terminal and the ground voltage supply terminal. This capacitor charges and discharges to provide an output voltage VOUT. A pull-up transistor can be provided to help pull the output terminal up toward a voltage equal to a VCC supply voltage minus the threshold voltage of the pull-up transistor.
A discharging transistor is coupled between the first node and a ground voltage supply terminal. The gate of the discharging transistor is coupled to receive a discharge enable signal (DIS) from the charge pump. In one embodiment, the discharging transistor is an NMOS transistor.
During a first period of a charging cycle, the charging voltage VCH is asserted at the high value of VCHxe2x80x94MAX, and the switching voltage VSW is asserted low, such that the first and second PMOS transistors are turned on, and the capacitor charges. The first PMOS transistor is sized to have a relatively high on-resistance compared to the second PMOS transistor. As a result, the charging current is minimized, thereby minimizing the drain-to-source voltage drop across the second PMOS transistor to a voltage less than a junction voltage drop. Consequently, the drain-to-bulk junction of the second PMOS transistor is not forward biased during the first period of the charging cycle. The first and second PMOS transistors enable the voltage applied to the capacitor to be approximately equal to VCHxe2x80x94MAX. As a result, the output voltage VOUT can advantageously approach the breakdown voltage of the PMOS transistors.
During a second period of the charging cycle, the discharge enable signal DIS is asserted high, thereby turning on the discharging transistor coupled to the first node, and causing the first node to discharge. Because the drains of the first and second PMOS transistors are coupled to the first node, the drain-to-bulk junctions of the first and second PMOS transistors are prevented from being forward biased during the second period of the charging cycle.
The present invention will be more fully understood in view of the following description and drawings.